An input/output buffer circuit is a circuit for transmitting and receiving a chip-to-chip signal, and has various shapes according to a type of a system used.
In general, for exchanging the chip-to-chip signal, a voltage level may be greater than a power source voltage used within the chips.
The voltage level exceeds a voltage allowable for a single stage of transistors, and thus the voltage should be distributed using several stages of transistors.
There may be present a block (or circuit) for generating a necessary bias within an input/output circuit, in order to stably distribute the voltage.
An input/output circuit having a fail-safe function is an input/output circuit which is prepared for a case where there is any one chip (or a chip required for a fail-safe operation) without power supplied thereto in a system, namely, a case where the aforementioned bias circuit does not operate due to non-presence of a power supply in the input/output buffer circuit.
FIG. 1 is a circuit diagram illustrating a digital input/output circuit having a typical type of a fail-safe function.
As illustrated in FIG. 1, an input/output (I/O) circuit may include an IO driver block 20 for outputting an IO voltage, an electrostatic discharge (ESD) protection circuit 30, and a bias generator block 10 for performing a fail-safe operation.
Transistors constructing the input/output circuit should be used at a voltage of 2V or less during process, and an input/output voltage of 3.3V is assumed.
For the fail-safe operation, under a situation that a voltage of a power source is 0V (VDDPST=0) and a voltage of a pad PAD of 3.3V is applied, a voltage of a first bias BIAS1 should be generated to correspond to a half level of the voltage of the pad PAD so as to be less than 2V which is an allowable value of a voltage applied to MNB1.
A second bias voltage BIAS2 should be biased to 3.3V which is the same as the voltage of the pad in order to prevent a flow of current in a reverse direction, namely, to a direction toward the VDDPST due to a reverse turn-on of Mpb1. Or, the second bias voltage BIAS2 should be biased to 3.3V which is the same as the voltage of the pad in order to meet the allowable voltage of Mpb1.
NWBIAS of 3.3V which is the same as the voltage of the pad PAD should be applied to prevent a turn-on of a junction diode between a drain terminal and a bulk (or a body) of Mpb1.
Hereinafter, a problem of the related art bias generation circuit will be described, for example, based on the first bias voltage BIAS1.
When desiring to generate a half voltage by using the voltage of the pad as a power supply (or a power source), similar to a bias1 generator 10 illustrated in FIG. 1, diodes are disposed in series to generate an intermediate voltage.
In an ideal manner, a stabilized voltage of the first bias BIAS1 may be generated by always maintaining it to be the same as about 0.5*PAD voltage.
The diode-type voltage distribution method used herein generates a bias required for the fail-safe operation by consuming a predetermined current from the pad. Therefore, the voltage distribution method is subject to a restriction that such current should be below a predetermined level.
For an input/output circuit with a great load which results from a size of a transistor constructing a circuit such as an electrostatic discharge (ESD) or the like, a predetermined time is generally required for generating the bias using such small current. This may bring about a restriction of an operation speed of the input/output circuit.
FIG. 2 is a conceptual view illustrating an affection of parasitic capacitor components in a typical bias generating circuit.
As illustrated in FIG. 2, when an input/output signal is fast, it is necessary to take into account parasitic components present within the input/output circuit.
A driver and an ESD circuit present within the circuit may use a transistor with a great width for the purpose of driving a great current, and have a great parasitic capacitor.
Regarding the parasitic capacitor, as illustrated in FIG. 2, a high frequency path from the pad to a node of the first bias may be created by the parasitic capacitor.
Therefore, at the moment when the pad PAD fast changes from 0V to 3.3V, the voltage of the first bias BIAS1 may be more than 2V which is an allowable voltage value of the transistor.
To prevent this, a method of restricting a voltage by applying a diode with a great capacity to the node of the first bias may be considered.
However, a generally-used diode is difficult to generate various levels of voltages because of a great threshold voltage of 800 mV. The threshold voltage may make it difficult to stably restrict a voltage due to its unstable changes depending to processes.